Image sensors may be semiconductor devices that convert optical images into electrical signals. Among various image sensors, a CMOS image sensor may be a device that uses a switching mode to sequentially detect an output by providing photodiodes corresponding to the number of pixels through a CMOS technology that uses peripheral devices, such as a control circuit and a signal processing circuit.
A CMOS image sensor may include photodiodes that may sense light. A CMOS image sensor may further include a CMOS logic circuit to process the sensed light, and convert it into electrical signals. The detected light may thereby be represented as data. To improve the photosensitivity, the area occupied by the photodiodes may be increased with respect to the whole area of the image sensor area, or a photo-gathering technology may be used to collect more light in the photodiode area, for example by reducing the light path and/or forming a micro-lens on an upper portion of the photodiodes.
A CMOS image sensor may be divided into various types according to a number of transistors. For example, a CMOS image sensor may be a 3T-type CMOS image sensor, a 4T-type CMOS image sensor, or a 5T-type CMOS image sensor in accordance with the number of transistors. A 3T-type CMOS image sensor may have one photodiode and 3 transistors. A 4T-type CMOS image sensor may have 4 transistors.
FIG. 1 is an example equivalent circuit diagram of a related art 3T CMOS image sensor, and FIG. 2 is an example layout diagram illustrating a unit pixel of the related art 3T CMOS image sensor.
Referring to FIG. 1, the unit pixel of a related art 3T-type CMOS image sensor may include one photodiode and three nMOS transistors T1, T2, and T3. The cathode of photodiode PD may be connected to the drain of first nMOS transistor T1 and the gate of second nMOS transistor T2.
In addition, sources of first and second nMOS transistors T1 and T2 may be connected to a power line that may provide reference voltage VR. A gate of first nMOS transistor T1 may be connected to a reset line that may provide reset signal RST.
The source of third nMOS transistor T3 may be connected to the drain of the second nMOS transistor. The drain of third nMOS transistor T3 may be connected to a reading circuit (not shown) through a signal line. The gate of third nMOS transistor T3 may be connected to a column selection line to which the selection signal SLCT may be supplied.
First nMOS transistor T1 may be referred to as reset transistor Rx, second nMOS transistor T2 may be referred to as drive transistor Dx, and third nMOS transistor T3 may be referred to as selection transistor Sx.
Referring to FIG. 2, in a unit pixel of the related art 3T CMOS image sensor, active region 10 may be defined so that one photodiode 20 may be formed in a wide part of active region 10 and gate electrodes 120, 130, and 140 of the overlapping three transistors may be formed in the remaining part of active region 10.
That is, reset transistor Rx may be formed by gate electrode 120, drive transistor Dx may be formed by gate electrode 130, and selection transistor Sx may be formed by gate electrode 140.
Dopants may be implanted into the part excluding the lower parts of gate electrodes 120, 130, and 140 in active region 10 of the transistor, so that the source and drain regions of the transistors may be formed.
Accordingly, supply voltage Vdd may be applied to the source/drain area between reset transistor Rx and drive transistor Dx, and a source/drain area formed at one side of the select transistor Sx may be connected to a reading circuit (not shown).
Although not shown in the drawing, gate electrodes 120, 130, and 140 may be connected to the signal lines and each signal line may include a pad at one end which may be connected to an external driving circuit.
Hereinafter, a method of manufacturing a related art CMOS image sensor will be described with reference to the attached drawings.
Referring to FIG. 3A, dopants may be selectively implanted into semiconductor substrate 31 so that R-photodiode 81 and G-photodiode 82, that may be respectively configured to sense red and green signals, may be formed in the photodiode region to have different depths.
A prescribed portion of semiconductor substrate 31 may be etched using a hard mask (not shown) such as a nitride layer. This may separate a peripheral circuit region and a pixel region from each other to form a trench. An oxide layer may be deposited to be buried in the trench, and the surface may be planarized, for example by a chemical mechanical polishing (CMP) method, to form a shallow trench isolation (STI) 32.
P-well region 51 may be formed in a region of the pMOS of semiconductor substrate 31 adjacent to where STI 32 may be formed. Gate oxide layer 41 and gate 42 may be sequentially formed on the semiconductor substrate. Low density n-type impurities may be ion implanted into a prescribed portion, for example by a blanket ion implantation method. N-type LDD region 43 may thus be formed in the nMOS transistor region.
First photoresist pattern 91 may be formed so that only the pMOS region may be exposed and low density p-type impurities may be ion implanted using gate 42 as a mask to form p-type LDD region 53 in the pMOS transistor region.
Referring to FIG. 3B, second photoresist pattern 92 may be formed so that only the photodiode region may be exposed and n-type impurities may be ion implanted to form B-photodiode 83.
Referring to FIG. 3C, an oxide layer may be deposited on a surface (for example, on the entire surface) of semiconductor substrate 31 and an etchback process may be performed on the surface to form side wall spacers 40, that may be connected to the sidewalls of gate 42.
Third photoresist pattern 93 may be formed so that only the photodiode region may be exposed and p-type impurities may be ion implanted to form p-type impurity region 83a in B-photodiode 83. Accordingly, the buried B-photodiode may be completed.
Referring to FIG. 3D, a surface of semiconductor substrate 31 may be coated with photoresist (not shown). Patterning may be performed so that only the nMOS transistor region may be exposed, and the n-type impurities such as arsenic (As) may be ion implanted to form n-type source and drain region 44.
Finally, the photoresist may be removed, another photoresist may be applied, patterning may be performed such that only the pMOS transistor region may be exposed, and p-type impurities such as boron (B) may be ion implanted to form p-type source and drain region 54.
Hence, n-type source and drain region 44 and p-type source and drain region 54 may have narrower areas than n-type LDD region 43 and p-type LDD region 53 by the width of side spacers 40.
However, the related art method of manufacturing the CMOS image sensor described above may have various problems.
For example, to form the buried photodiode, the deep n-type impurity region may be used to form the B-photodiode, sidewall spacers may be formed on the adjacent gate sidewalls, and the p-type impurity ion may be implanted into the surface of the n-type impurity region to complete the buried photodiode. To form a buried photodiode, a PDP process of implanting the p-type impurity ion may be added. This may be a complicated process.
Furthermore, after forming the side spacers, the p-type impurity region may be formed. Current may leak under the side spacers. In the related art technology, there may be limitations on solving the problem of leaking the current.